Analysis on the impact of interface Trap distributions on SOI DMG FinFETs: Overlap/underlap configurations

Abstract

This paper investigates the significance of interface trap charges (ITCs) distribution by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator on dual-material gate (DMG) FinFETs in gate Overlap and Underlap configurations in terms of DC and analog/RF parameters. Different charge density profiles like Uniform and Gaussian distribution of traps are considered at different energy levels for both donor and acceptor ITCs to evaluate the devices reliability. It is observed that the donor traps mainly affects the OFF-state current (IOFF) by insignificantly, while, acceptor traps mainly impacts ON state current significantly. The impact of Acceptor ITCs on various parameters such as transfer characteristics, electron density, conduction band energy, transconductance (gm), total gate capacitance (Cgg), device efficiency (gm/ID), and cut-off frequency (fT), for DMG FinFETs have been comprehensively analysed at trap concentration N0=1×1013 and compared with no traps among the three devices. An acceptor trap charges with Gaussian distribution has larger impact on devices performance. It degrades the ON state-current by 36.09 %, 25.72 %, and 41.9 % for conventional, Overlap, and Underlap configurations, respectively. It is evident from the results DMG underlap configuration is more vulnerable to ITCs, attributed to its larger interface charge region due to the increase in effective channel length while, the overlap configuration is more immune towards ITCs as, lesser electrons get trapped. Thus, the overlap configuration is the most reliable among underlap and conventional configurations.