Performance Analysis of Different Multipliers using Square Root Carry Select Adders

Abstract

A high-speed and energy-efficient multiplier is always required in electronics industry particularly in digital signal processing, arithmetic units in microprocessor and image processing. Multiplier is a significant element which contributes to the total power utilization of the system. By comparing different types of adders it is found that the ripple carry adder has a smaller area with lesser speed performance, in contrast to which carry select adders have high speed but posses a larger area. In the existing models of the multipliers, the regular square root carry select adder and modified square root carry select adder using Binary to Excess-1 logic are designed and implemented on both Array and Wallace tree multipliers respectively. In the proposed work a proficient square root carry select adder is designed using common Boolean logic and is implemented on both Array and Wallace tree multipliers respectively. A well-organized Verilog code has been written and successfully synthesized and simulated using Xilinx ISE 14.2. The simulation results gives the performance of Array and Wallace tree multipliers using proposed square root carry select adder is excellent compared with other structures of square root carry select adders.