Abstract
This paper presents a PDK design in 0.13um SOI process provided by GSMC Corporation as well as a LDO design in This PDK. PDK (Process Design Kit) for analog/mixed-signal IC design provides a complete set of design documents, which is a connection between the integrated circuit and integrated circuit technology manufacturing complete data platform.[1] This article uses the GTE tools provided by Cadence to complete the design of CDF, layout and technology file. Some corresponding optimization was utilized to fit the characteristics of the SOI technology. Finally, this paper introduces a LDO design using this PDK suite which demonstrated the feasibility of this PDK design.
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