Layout Test Structures for Custom Analog Blocks

Abstract

For some complex mixed-signal Integrated Circuits (ICs) testing for quality assurance is approaching the manufacturing costs. Mixed Signal IPs have Analog and Digital building blocks which are integrated to create a top-level IP block. Analog building blocks use variety of active and passive devices which will have different design rules to be followed to meet the manufacturing requirements. With lower process node, the number of design rules is increasing exponentially. These rules put lots of constraints on device placements. Lack of layout designs in the early phase of new process nodes inhibits the layout designers to validate all the design rule requirements and the violations are found later in the design cycle. Every time a new Process Design Kit is released with new design rules, the layout design teams have to validate the changes on live designs leading to lost design cycles. One of the solutions involved is to create layout test structures using different device types with all combinations available on a given process node and test structure to test integration guidelines given by SoC. These test structures will enable layout designers to qualify the design rules and then identify the valid placement and integration specifications. These can also be used to Quality Assurance (QA) of new Process Design Kit(PDK) before providing PDK to the design engineers. This will reduce the overall design cycle time by testing the design kits and provides guidelines to the layout designers for creating the layouts.