Parameter sensitivity for optimal design of 65 nm node double gate SOI transistors

Abstract

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length Lg reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of the gate delay and on–off current ratio to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulations. The impact of the spacer length and doping gradient to the device and circuit performance are comprehensively investigated. It was found that the HP and LOP DGSOI could achieve the ITRS specification with a wider range of parameter combinations than the LSTP.