Page-Based Dynamic Partitioning Scheduling for LDPC Decoding in MLC NAND Flash Memory

Abstract

To increase program-and-erase (PE) cycles for the multi-level-cell NAND flash memory, a page-based dynamic partitioning scheduling (DPS) algorithm for low-density parity-check codes is proposed in this brief. The proposed scheme provides a dynamic scheduling metric to obtain variable nodes (VNs) with the highest erroneous probabilities in each iteration so as to improve the convergence speed of decoding. Then, two DPS-based belief-propagation (BP) and min-sum (MS) decoding algorithms are introduced, named DPS-based BP (DPS-BP) and DPS-based MS (DPS-MS), respectively, which utilize the interaction between the upper page and the lower page bits to detect the probable charge-shift memory cells. Simulation results show that the proposed DPS-BP and DPS-MS decoding algorithms improve the PE endurance up to about 700 and 1000 cycles against the conventional BP and MS decoding algorithms, respectively, at a bit-error-rate of ${10}^{{-5}}$ . In addition, an effective approximation method is presented to reduce the hardware complexity in practical implementations, in which the size of each partitioned group is preset to raise the efficiency of the VN units.