Oxide semiconductors for advanced CMOS

Abstract

Oxide semiconductors have emerged as appealing alternatives for back-end-of-line (BEOL) compatible channel transistors in advanced CMOS applications. As technology advances, the demands for semiconductors with faster processing speeds, higher density, and lower power consumption increase. Current CMOS technology struggles to keep pace with these evolving demands mainly because of the fundamental physical limitations which result into new state-of-the-art concepts such as stacking up devices from two-dimensional (2D) planar structure to 3D stacked structure. To realize such vertical integration based on oxide semiconductors, high performance i.e., good carrier mobilities (∼ 50cm2/V.s), wide bandgap (>1.1eV), ultrahigh scalability (Lg<50nm and thickness ≤ 10nm), extremely low off-state current (1fA) and superior ION/OFF (∼ 108–1011) in suitable p-type and n-type oxide TFTs are required. In this chapter, following a brief introduction of oxide semiconductors in advanced CMOS application, design strategies for hole dopable p-type oxide are summarized based on Sn/Pb s−O 2pz hybridization in the Sn2+−O−X and Pb2+−O−X systems, interlayer and amorphous-crystalline phase engineering. Furthermore, the fundamental concept of charge transport mechanisms in crystalline phases is introduced. Later, a brief discussion on n-type oxides, specifically focused on amorphous oxide semiconductors (AOS), is provided, along with relevant discourse on current research trends, challenges, and mobility prediction models within amorphous structures. This chapter explores the design strategy aimed at enhancing the performance of both p-type and n-type oxide semiconductors for advanced CMOS applications, offers an overview of the present status of promising candidates and provides insights into boosting performance metrics from both theoretical and experimental perspectives.