Abstract

The current electronic device scaling is reduced to 5 nm and smaller technology nodes based on EUV lithography, it is expected to reach sub-nm technology node within a decade. Along with the EUV scaling, the space of medium/upper level BEOL provides both challenges and opportunities to device research community. Rational design of device materials using atomic scaling modeling methods can contribute the accelerated development of the new technology materials based on fundamental understanding on their atomic and electronic scale properties. Using the density functional theory (DFT), atomistic kinetic Monte Carlo (KMC) and time-dependent DFT (TDDFT) simulations methods, we have been investigating the BEOL process compatible oxide semiconductors for monolithic 3 dimensional (M3D) integration of functional devices in the intermediate interconnect layers. In this tutorial, we will discuss about the multiscale modeling approaches applied to device materials modeling for n- and p-type oxide semiconductor design for BEOL applications. We will examine atomic and electronic structures of both n-type and p-type oxide semiconductors in crystalline and amorphous phases. Using the rational design approach to oxide semiconductors based on DFT calculations, we are exploring the complex oxide material parameter space and charting possible pathways to develop both p-type and n-type oxide semiconductor candidates for BEOL CMOS applications. We will discuss the design rationales of currently identified oxide semiconductor candidates (Ta2SnO6, TiSnO3 for p-type In-W-O system for n-type) and validation experiments to accelerate the focused development of BEOL oxide semiconductors with superior performance. These oxide semiconductors will provide case study examples of the materials deign method applied to electronic device materials in this tutorial. This work was supported by ASCENT, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

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