(Invited) P-Type Thin Film Oxide Semiconductors for Thin Film Transistor-Based CMOS Logic

Abstract

The development of products, and perhaps most notably displays, which rely on thin film transistors (TFTs) has been enabled by the availability of high quality, thin film semiconducting materials. Hydrogenated amorphous silicon (a-Si:H) was the first such material to meet the demands of the display industry. Other materials have since also gained importance including polycrystalline silicon, organic semiconductors and, most recently, oxide semiconductors. In this latter case, indium gallium zinc oxide (IGZO) has been successfully commercialised at scale. However, TFT circuits using any of these materials are based on NMOS or PMOS logic rather than CMOS preventing their use where low power consumption is essential such as display driving circuits, memories or logic as it has not proved to be possible to produce n-channel and p-channel TFTs with sufficiently similar performance characteristics in one material system. In the case of the thin film silicon-based materials, this is because the hole mobility is much lower than the electron mobility, whilst in organic semiconductors it is the p-type materials that are superior to the n-type. In this paper, the situation in oxide semiconductors is considered in detail.There are several oxide semiconductors which have been used to make excellent TFTs, perhaps most notably amorphous (a-)IGZO and amorphous zinc tin oxide (a-ZTO). Both of these materials are naturally n-type as their charge neutrality level is close to the conduction band edge. As a result, it has not proved to be possible to successfully introduce sufficient acceptor-type impurities in order to stably produce a p-type behaviour in these materials; completely different p-type thin film oxide semiconductors are therefore required. Cuprous oxide (Cu2O) is one such material, and this will be used as an exemplar in this work, although alternatives such as tin oxide (SnO) and nickel oxide (NiO) have also been reported.This move to alternative material systems presents other challenges. The conduction band minimum in n-type oxides is dominated by spatially extensive and spherically symmetric metal s-shell electron orbitals, and this allows an amorphous phase to be induced by stoichiometry control of oxide semiconductor which has no grain boundaries and is highly uniform but which retains a high electron mobility. However, the valence band maximum in the p-type materials is dominated by oxygen 2p-orbitals (sometimes with metal d-orbital hybridisation is found in Cu2O) which are highly directional. This means that any attempt to introduce an amorphous microstructure would result in a significant reduction in hole mobility compared with the crystalline state (it is this effect that is responsible for a-Si:H having an electron mobility that is 1,000 times lower than its crystalline counterpart).The types of deposition techniques (most commonly sputtering) that are used to produce thin film oxide semiconductors do not permit the production of single-crystalline thin film materials; nanocrystalline microstructures are created instead. This leads to the presence of grain boundaries, which are highly problematic as they contain a high density of defect states. As a result, they act as trap sites for holes and significantly reduce carrier mobility compared with the single crystal state. Some degree of mitigation is possible by controlling grain orientation during growth, and for Cu2O it is possible to select either the (100) or (111) orientation [1]. Grain size may also be increased and boundary defects decreased after growth by annealing [2]. The result is TFTs with a significantly lower field effect mobility (typically less than 1 cm2 V–1 s–1) than is found in the n-type oxide TFTs (typically over 10 cm2 V–1 s–1). Furthermore, these defective grain boundaries can allow the accumulation of electrons in the off-state leading to much higher off-state currents than would be expected [3]. As a result the switching ratio of p-type oxide TFTs is much lower (typically less than 103) than in equivalent n-type devices (>107).Despite these limitations, it is still possible to combine p-type and n-type oxide TFTs to make CMOS logic gates, but it is important to consider carefully the application requirements and the associated compromises that must be made in circuit design.The funding for this work by the Engineering and Physical Sciences Research Council through grant numbers EP/M013650/1, EP/P027032/1 and EP/L015455/1 is gratefully acknowledged.[1] Han, S. and Flewitt, A.J., Thin Solid Films, 704, 138000 (2020)[2] Han, S., et al., Appl. Phys. Lett., 109, 173502 (2016)[3] Han, S. and Flewitt, A.J., IEEE Electron Dev. Lett., 28, 1394 (2017)