Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

Eduardo Pérez,Christian Wenger,Francisco Jiménez-Molinos,Rocío Romero-Zaliz,Antonio Javier Pérez-Ávila,Emilio Pérez-Bosch Quesada,Juan Bautista Roldán,Mamathamba Kalishettyhalli Mahadevaiah

doi:10.3390/electronics10091084

Abstract

Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.

Highlights

Introduction iationsSince the IBM supercomputer Deep Blue was able to defeat the world chess champion Garry Kasparov in 1997 [1], the artificial intelligence (AI) field has experienced a dramatic boost
The strategy followed by the multi-level incremental step pulse with verify algorithm (M-ISPVA) to program resistive random access memory (RRAM) devices is to apply a sequence of voltage pulses to the RRAM devices, which features a constant increment in amplitude [32]
After applying the forming operation in three steps, the experimental read-out current distributions obtained for the four conductive levels, namely, high resistive state (HRS), LRS1, LRS2, and LRS3 by using the optimized combination of M-ISPVA parameters are shown in Figure 2a,b as histograms

Summary

Experimental Methodology

The whole experimental characterization was carried out by switching the RRAM devices integrated in a 4-kbit memory chip (Figure 1, right) in order to assess the DTD variability within an architecture comparable to a real hardware accelerator. The strategy followed by the M-ISPVA to program RRAM devices is to apply a sequence of voltage pulses to the RRAM devices, which features a constant increment in amplitude [32] This sequence is applied on the bit line (BL) terminal during forming and set operations, whereas it is applied on the source line (SL) terminal during reset operations (Figure 1). The role of both Itrg and Vg parameters is slightly different The former limits the maximum current value of the high resistive state (HRS), whereas the latter is defined with a value that minimizes the series resistance of the transistor. The CTC variability associated with the RRAM devices under study was evaluated by means of two types of tests: a collection of switching cycles between all possible LRS-LRS combinations (passing through the HRS) in the same batch of 128 RRAM devices (inter-levels switching) and an endurance test of one thousand (1 k) reset-set cycles between all three HRS-LRS combinations

Modeling Methodology

Experimental and Modeling Results

VMM Architecture and Operational Results

DNN Implementation

Findings

Conclusions