A Mixed-Signal Convolutional Neural Network Using Hybrid CMOS-RRAM Circuits

Abstract

Hybrid integration of the resistive Random Access Memory (RRAM) arrays with standard CMOS has gained recent attention for realization of neuromorphic computing hardware. Such architectures are expected to result in orders of magnitude higher energy-efficiency than their digital counterparts. While a few fully-connected neural networks have been realized using RRAM arrays, a parallel hardware implementation of convolutional neural networks (CNNs) has lagged due to the sequential nature of processing. Prominent reasons include high device variability, lower yield of fabricated 1T1R RRAM devices, and the challenges associated with the retention of multi-levels states in RRAM synapses due to their resistance drift. In this work, we propose and analyze a hybrid solution where constant-g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> CMOS-RRAM cells hold the kernel weights and CMOS mirrors are used for Spiking Neural Network (SNN) processing. This is in contrast with the approaches where all weights are implemented using individual 1T1R cells, or addressing is used to route spikes to an SNN that only implements the CNN kernel.