Optimization of Halo Implant Using 3D TCAD for Nanoscale MuGFETs

Abstract

This work presents a theoretical design analysis of halo implants for n-MuGFETs using commercial three-dimensional (3D) TCAD simulation tool. The main objective was to show feasibility of a three-dimensional (3D) process simulation within the context of optimization of the device design and the underlying fabrication processes. The 3D simulation process flow is based on the development of the SOI based FinFET devices. Process and device simulations of halo implants have been performed with different nitride spacer, fin thicknesses and gate lengths. We see that thick nitride spacers (50 nm) and thinner fins (30 nm) are beneficial for 80 nm doped channel n-MuGFETs. Similarly, the role of halo implant is critical to suppress the short channel effects for small gate lengths (65, 50 nm etc) devices. Although, the halo implant is beneficial to adjust the threshold voltage to a required value, its presence is counter productive from the point of view of degradation in ION particularly for long channel devices. Using pre-development process results of our MuGFETs, good agreement was obtained with simulations and experimental data in terms of threshold voltage roll-off, ION/IOFF and short channel effects