Abstract
This work deals with the junction and channel optimization on FinFET devices. The main objective was to show feasibility of a three-dimensional (3D) process simulation within the context of optimization of the device design and the underlying fabrication processes. The 3D simulation process flow is based on the development of the SOI based FinFET devices at Infineon. Similar to real devices, important 3D geometrical features, such as corner roundings and 3D facets have been introduced into the simulation setup, which is based on commercially available 3D process simulation software (Taurus 3D). The influence of various unit process steps, such as channel implant, and LDD implant on the electrical performance of the devices have been evaluated. Beside the successful demonstration of a functional 3D process simulation flow, detailed issues of process and device simulation methodology such as the usage of different dopant diffusion and mobility models are assessed. Finally, a comparison of the simulation results with electrical measurement data is performed which fairly shows excellent agreement.
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