Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell

Abstract

The stability, leakage power and speed of Static random access memory (SRAM) have become an important issue with CMOS technology scaling. In this paper, a controller circuit is introduced which is separately controlling the load, driver and access transistors of SRAM cell. Based on word line signal value, optimal body bias voltage is generated through control circuitry to control stability, leakage and speed in SRAM cell. The proposed cell gives faster read and writes with an improvement of 68.5% and 89.2% over conventional 6T SRAM cell. In standby mode, about 62.2% leakage power reduction is observed in [Formula: see text] array architecture of SRAM. The proposed cell is implemented with 65[Formula: see text]nm CMOS technology and exhibits higher hold and write margins with an improvement of 26.29% in hold margin and 16.6% improvement in write margin as compared to conventional 6T SRAM cell. Robustness of the proposed SRAM cell with respect to stability, leakage and speed are confirmed under process, voltage and temperature variations.