On the use of fully specified initial states for testing of synchronous sequential circuits

Abstract

Full scan design renders every combinationally irredundant fault in a synchronous sequential circuit testable. In this paper, we derive a similar result applicable to design-for-testability techniques that only controls the initial state of the circuit in order to improve its testability. Examples of such techniques are parallel load, reset, and scan when it is used only to set the state of the circuit. We show that if the initial state can be set arbitrarily, a test sequence can be generated for every irredundant fault, i.e., for every fault that is not sequentially or combinationally redundant. Thus, the ability to control the state of the circuit is sufficient for detecting every irredundant fault and observability of the circuit state is not necessary for this purpose. When considering scan, this result implies that scan-out can be used to control the test length and test generation time, but it is not necessary for detecting irredundant faults. We also show that, of all the states of the circuit, it is sufficient to consider as possible initial states (or controllable states) only the states extracted from a complete combinational test set. We demonstrate the use of these observations by presenting experimental results of two applications. In the first application, initial states are selected out of a combinational test set to facilitate deterministic test generation for irredundant faults. In the second application, the ability to set the initial state is used to increase the effectiveness of built-in self-test.