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https://doi.org/10.1049/el:19880382
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Cite Journal: Electronics Letters |  Publication Date: Apr 28, 1988 |
 Citations: 13 |
Affiliation: Linköping University
We propose that a special interconnection metal layer is introduced into the VLSI process and used for global clock distribution and communication. We show that by this method the interconnection delay will not be a limiting factor for the speed of synchronous circuits in CMOS down to 0.3 μm feature sizes and up to 20 mm chip sizes.
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