Abstract
A lightly doped drain (LDD) region, particularly a gate-overlapped LDD (GOLD) region, is subjected to a gate electric field and its gate-controlled resistance affects the device characteristics. We developed a new extraction method for determining the intrinsic characteristics of LDD MOSFETs using a simple series resistance model, in which the GOLD region is assumed to be a depletion MOSFET with a negative threshold voltage derived from C–V measurement. Polycrystalline-silicon (poly-Si) TFTs with a channel length of 4–100 µm were used for the test LDD samples, particularly GOLD MOSFETs. It was demonstrated that the new proposed method precisely extracts the intrinsic characteristics of poly-Si GOLD TFTs by comparing them with the intrinsic characteristics of poly-Si Self-Aligned (SA) TFTs extracted by the conventional method.
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