Abstract

An in-situ doped polysilicon emitter process for very shallow and narrow emitter formation and minimum emitter resistance is presented. An in-situ doped film was imbedded between two undoped poly spacer layers as a buried diffusion source (BDS) to reduce the emitter resistance and to form a high-quality poly/monosilicon interface. Transistors with an emitter area of 0.25 mu m*0.25 mu m and with nearly ideal I-V characteristics were fabricated. A cutoff frequency of 53 GHz and a minimum ECL gate delay of 26 ps were achieved using BDS poly emitter transistors with an emitter area of 0.35 mu m*4.0 mu m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

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