Abstract

An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous SiGe HBT developments originates primarily from an optimized vertical profile, an additional decrease of the base and emitter resistance which is made possible by combining millisecond annealing with a low-temperature backend, and from lateral device scaling.

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