15-ps ECL/74-GHz f/sub T/ Si bipolar technology

Abstract

A very high performance Si bipolar transistor technology has been developed. In-situ phosphorus doped polysilicon (IDP) emitter technology was used to reduce the thermal budget and emitter resistance. Very thin bases were obtained by rapid vapor-phase doping (RVD) and low energy BF2/sup +/ ion implantation. Double-polysilicon self-aligned bipolar technology with U-groove isolation on bonded SOI wafers was used to reduce the parasitic capacitances. Using these key techniques, a minimum ECL gate delay time of 15 ps and a cut-off frequency of 74 GHz have been achieved. >