A 0.5- mu m very-high-speed silicon bipolar devices technology U-groove-isolated SICOS

Abstract

A 0.5- mu m high-performance silicon bipolar technology is developed and a very-high-speed emitter-coupled-logic (ECL) circuit is demonstrated. Circuits are fabricated with a 0.5- mu m SICOS (sidewall base contact structure) technology featuring U-groove isolation, a shallow impurity profile, and reduced base resistance. A U-groove-isolated SICOS structure is realized by the new self-alignment technology using the double polysilicon planarization method. To reduce the extrinsic base resistance, a large-grain base polysilicon is grown from the amorphous silicon layer. A greatly reduced substrate capacitance and small base resistance are obtained. Using these technologies, a minimum ECL gate delay of 27 ps at F/sub in/=1 is realized. A 20-ps ECL gate will be possible in a device having a smaller emitter and the optimal graft base depth. >