Novel Design of High Speed 64 bit Optimized MAC Unit

Abstract

In the present-day, the never-ending demand of the digital processor has been magnifying the ability of the processor to operate the difficulty developed in the integrated chip. To decrease the size of the computer day by day increases the load of the processor. This load may slow down the core processor. This load can be minimized by the co-processor, which is added within the core processor. These are made up of work with particular type functions like DSP, DFT, DCT, etc. So that the MAC unit is the most efficient co-processor. MAC unit consists of a multiplication and accumulation unit. Overall execution speed and performance of entire computing based on the time delay of the multiplication and addition. Multiplication plays an important role to determine all total performance of the MAC unit. Multiplication is a good familiar architecture of shift and adds algorithm which is considered as a chain of replicate addition of partial product. In this display paper work in 64 bit Booth multiplier. Booth multiplication is a high-speed algorithm, and multiplier occupies less area, and consume low power. The proposed multiplier is capable to multiply both negative and positive numbers. In the display, the paper introduces data path and controller to increases the speed and decreases the delay.