An Efficient Design and Implementation of High-Speed Booth Multiplier using Shift-Opt Algorithm

Abstract

In the Digital Signal Processing systems, multiplier plays vital role and form a basic block in every ALU and MAC units. An effective multiplier is designed by considering certain parameters such as speed, power consumption, area requirement and complexity. Among various multipliers, Booth multipliers have an advantage of reducing partial product stages and operate at moderate speed. The conventional booth multiplier uses separate registers to hold multiplier, multiplicand, product and partial product values. This paper is presented to improve the computation time of the Booth multiplier using Shift-Opt algorithm. The algorithm detects the sequence of zero recoding bit pairs and non-zero recoding bit pairs of the multiplier using the Bit Pair Detector (BPD). The output obtained from the Bit Pair Detector decides which operation to perform and hop between the functional blocks. In the proposed system, the multiplier value is assigned to the product register itself for effective hardware optimization. The design of the Bit Pair Detector is simple. The algorithm can be applicable to all the radix schemes (i.e. radix-2, radix- 4, radix- 8 and so on). Thus, it will greatly reduce the transition delay, increases the efficiency of the multiplier, provides better area-time performance and accuracy. In Verilog HDL 32 bit multiplier is configured, and it is simulated using Xilinx ISE. It is shown that for the bit width of 16, our optimization has resulted in 28.46% improvement over the existing Modified Booth multiplier by means of delay, based upon the input set.