A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier

Abstract

In this paper, a reconflgurable multi-precision Radix-4 Booth multiplier structure is presented. The reconfig- urable 8 x 8 bit multiplier unit can be cascaded to form a multiplier that can adapt to variable input precision requirements. The number of bits can be extended by concatenating more stages together. For example, four 8 x8 bit units can be used to build a 16 x 16 bit Booth multiplier. In our proposed architecture, the multiplier adapts to different bit-lengths by using external control signals. The performance of our reconflgurable multiplier are compared with a parallel array multiplier and a conventional Booth multiplier. The comparison is based on synthesis results obtained by synthesizing all multiplier architectures targeting a Xilinx FPGA. The overhead resulting from our reconfiguration scheme are also evaluated and compared to a conventional Booth and array multipliers.