Notice of Violation of IEEE Publication Principles - A 10GHz SiGe OC192 frequency synthesizer using a passive feed-forward loop filter and a half rate oscillator

Abstract

Notice of Violation of IEEE Publication Principles<br><br>"A 10GHz SiGe OC192 frequency synthesizer using a passive feed-forward loop filter and a half rate oscillator"<br>by Maxim, A.<br>in the Proceeding of the 30th European Solid-State Circuits Conference, 2004. ESSCIRC 2004.<br>21-23 Sept. 2004 Page(s):363 - 366<br><br>After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.<br><br>Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:<br><br>C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik<br><br>Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.<br><br>Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.<br><br>Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.<br><br> <br/> A 10 GHz OC192 PLL frequency synthesizer was realized in a 0.25 μm SiGe BiCMOS process with 60 GHz transition frequency. Its phase noise was significantly reduced by using a half rate oscillator followed by a frequency doubler that alleviates the low quality factor of junction varactors at 10 GHz. A fully integrated loop filter was implemented using a passive feed-forward configuration, in conjunction with a Miller capacitance multiplier. A process and divider modulus independent PLL architecture keeps constant the phase margin, settling time and loop sampling ratio over design corners. The IC specifications include: 9.953/10.3125 GHz serial data rates, 155/622 MHz reference frequency, 5 mUI/sub rms/ serial clock random jitter, <8ps/sub p-p/ serial data deterministic jitter, 120 dBc oscillator phase noise at 100 kHz offset, 3-3.6 supply voltage, 1 W power dissipation and 2×2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area.