Notice of Violation of IEEE Publication Principles - A SiGe BiCMOS 9.75/10.6GHz Frequency Synthesizer for DBS Satellite LNB Down-Converters Using Half-Rate Oscillators

Abstract

Notice of Violation of IEEE Publication Principles<br><br>"A SiGe BiCMOS 9.75/10.6GHz Frequency Synthesizer for DBS Satellite LNB Down-Converters Using Half-Rate Oscillators"<br>by Maxim, A.; Gheorghe, M.; Turinici, C.;<br>in the Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2006<br><br>After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.<br><br>Specifically, the coauthor names were fabricated by Adrian Maxim and added to the paper. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:<br><br>C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik<br><br>Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.<br><br>Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.<br><br>Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references. <br/> A fully-integrated frequency synthesizer for DBS satellite front-ends was realized in a low cost 50GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> SiGe BiCMOS process. Two half-rate VCOs followed by Gilbert frequency doublers generate the 9.75/10.6 GHz LO signals with lower phase noise than a full-rate oscillator. The loop filter was integrated on-chip by using a passive feed-forward architecture that provides a noiseless resistor multiplication. A high PSRR regulator with a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> /R low noise reference was used to minimize the supply pushing impact on VCO phase noise and spur performance. The synthesizer performance includes: -106dBc/Hz phase noise at 100KHz offset, <0.4deg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> integrated phase noise, l times 1.9mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area and drawing 35mA from a 3.3V supply voltage