Non-equilibrium dielectric response of high-K gate stacks in Si MOSFETS: application to SO interface phonon scattering

Abstract

The problem of coupling between phonon and plasmon modes across the idealised gate stack of a semiconductor MOSFET with one or more high-K dielectrics has come under close scrutiny in the last few years. High-K dielectrics are a possible technology for achieving the same gate capacitance as with silicon dioxide but for a much thicker insulating region. The effect is to drastically reduce the gate leakage current which is driven by tunnelling. Unfortunately, the much higher values of the dielectric parameters leads to the emergence of soft optical phonons that give rise to strong electron-phonon scattering at the channel-dielectric interface. Even for perfectly flat interfaces with homogeneous dielectric layers the technical problem of determining the modes and scattering amplitudes for electron-phonon-plasmon interactions is formidable. Here the problem is briefly reviewed and an outline is presented of a computational scheme to describe the modelling of MOSFETs with realistic high-K gate stacks that are dominated by interface roughness a layer inhomogeneities. The long term objective is to build both ensemble Monte Carlo modelling schemes and non-equilibrium Green function schemes for this problem. Preliminary data based on the simplest version of the computational scheme leads to the conclusion that the inhomogeneities in the gate stack give rise to a inhomogeneous electron-SO phonon scattering amplitude across the channel where the amplitude is modulated by remote and near surface roughness and by the electron concentration and electron temperature across the channel. Polycrystallinity of the dielectric is shown to lead to strong device parameter variations across ensembles of devices. The presence of an interfacial silicon dioxide layer between channel and high-K dielectric leads to a decrease in SO phonon scattering rates and higher effective mobilities as a function of increasing interfacial layer thickness.