Interfacial Layer Engineering Using Thulium Silicate/Germanate for High-k/Metal Gate MOSFETs

Abstract

State-of-the-art CMOS technology employs high-k dielectrics in place of the conventional SiO2 and SiON gate dielectrics, due to the ability to achieve high capacitance density while guaranteeing sufficiently low leakage current density. Hf-based dielectrics are the most widely used high-k dielectrics in current CMOS technology and are usually deposited on top of an interfacial layer (IL), whose primary role is to provide good electrical quality of the interface with Si [1].A sub-nm chemical oxide (SiOx) or oxynitride (SiON) layer is typically employed as IL, although its relatively low dielectric constant hinders the long term scalability of the stack. It has however been shown that reducing or eliminating the IL has strong negative effects on device performance, therefore the IL thickness remains subject to a strict trade-off [2].An alternative approach consists in the integration of high-k interfacial layers, which can provide good electrical quality of the interface with the semiconductor while achieving very low IL EOT [3]. We have recently demonstrated a process module for integration of thulium silicate (TmxSiyO, “TmSiO” hereafter) as replacement for chemical oxide interfacial layer in a generic gate stack, providing interfacial layer EOT of 0.2±0.1 nm and interface state density lower than 2·1011 cm-2eV-1 at a total CET of >1.5 nm [4]. In this work TmSiO was integrated with HfO2/TiN gate stack to achieve a total EOT<1 nm.To evaluate the TmSiO/HfO2/TiN gate stack long channel P and NMOSFETs were fabricated using a gate last scheme with predefined dopant activated source and drain areas. The thermal budget was 400 °C after gate stack formation. Prior to gate formation the wafers were cleaned in H2SO4:H2O2 (3:1) and dipped in 5% HF followed by ALD Tm2O3 deposition at 250 °C using TmCp3 and H2O vapour as precursors [5]. A post deposition anneal at 550 °C for 60 s in N2 was employed to form a ~0.8 nm thick TmSiO layer. Unreacted Tm2O3 was stripped in H2SO4 with a selectivity of 23:1 towards TmSiO. HfO2 was deposited by ALD at 350 °C, using HfD04 and H2O vapor as precursors followed by post deposition anneal in ozone. Fig. 1 shows (a) schematically the TmSiO IL process and (b) a cross-section TEM of the complete gate stack. PVD TiN/TiW 15/100 nm was used as gate electrode. Ti/TiW/Al metallization and FGA (10% H2 in N2) ended the MOSFET fabrication.Excellent electron (~230 cm2/Vs) and hole mobility (~75 cm2/Vs) at EOT=0.8 nm and Ninv=1013 cm-2 was measured. These values represent a ~20 % improvement compared to SiOx/HfO2 gate stacks [2],[6]. The higher mobility possibly originates from the thicker physical thickness of the interfacial layer compared to SiOx interfacial layer for the same total EOT. Fig. 2 shows well behaved ID-VG curves for both P and NFETs with subthreshold slopes in the range 65-85 mV/dec.Given the excellent results of TmSiO interfacial layer on Si channel P and NFETs using HfO2/TiN as high-k/metal gate stacks, we investigate the potential for passivation of Ge MOSFETs using the same concept with the aim of forming thulium germanate (TmGeO) as an interfacial layer between the Ge channel and the high-k dielectric. Potentially the TmGeO interfacial layer can improve the scalability of GeO2 interfacial layer based gate stacks such as GeO2/Al2O3/HfO2 [7]. The formation of TmGeO is however not as straightforward as in the Si case, where the ALD growth of Tm2O3 was initiated on H-terminated Si surface. For Ge channel MOSFETs the Ge surface is not H terminated after HF etching but instead a relatively stable monoxide (GeO) exists on the Ge surface. Since GeO is insoluble in H2O it is challenging to completely remove it before ALD growth of Tm2O3. In our initial experiments we have found that annealing of Tm2O3 layers grown by ALD on HF-last Ge surfaces leads to inhibited formation of TmGeO. In this work we will report on various cleaning and pre-ALD treatments and their influence on the formation of TmGeO.REFERENCES[1] M. M. Frank, ESSDERC, 25-33(2011).[2] L.-A. Ragnarssson et al., Microelectron. Eng., vol. 88, no 7, 1317-1322, 2011.[3] T. Kawanago et al., IEEE TED, vol 59, no 2, 269-276, 2012[4] E. Dentoni Litta et al., IEEE TED, vol. 60, no 10, 3271-3276, 2013[5] E. Dentoni Litta et al., J. Electrochem. Soc., vol. 160, no 11, D538-D542, 2013[6] L.-A. Ragnarsson et al., VLSI_TSA, 2011[7] R. Zhang et al., IEEE TED, vol. 60, no 3, 927-934, 2013