Abstract
In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.
Highlights
Design of low power circuit is necessary for portable electronic devices that are powered by batteries as increased power dissipation reduces the battery lifetime
Subthreshold or weak inversion conduction current is the current flow between source and drain region in a MOS transistor, even when gate voltage, VGS is below the threshold voltage, VTH of the MOS transistor
Subthreshold leakage power reduction in standby mode is significant in burst mode type circuits, where computation occurs only during short burst intervals, and the system is in standby mode for the majority of the time [18]
Summary
Design of low power circuit is necessary for portable electronic devices that are powered by batteries as increased power dissipation reduces the battery lifetime. Subthreshold leakage current increases exponentially with the reducetion of the threshold voltage of the MOS transistor, making it critical for low voltage digital integrated circuit design. With rapid scaling in technology, the increase in leakage current has made leakage power a significant part in the overall power dissipation in both active and standby modes. Circuit techniques play a very important role to control the subthreshold leakage power dissipation in both active and standby modes. Already some techniques, such as Multi-threshold CMOS. Four new digital circuit design techniques namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique are presented These techniques are applied to a two input AND gate to evaluate their performance. It is found that the proposed techniques give improved performance in terms of reduced subthreshold leakage power dissipation in standby mode as compared with the other techniques available in the literature [8,9,10,11,12,13,14]
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