Near-Threshold Computing of Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Circuits

Abstract

Low-power design already becomes the main challenge in the modern VLSI design community. The voltage scaling technique has proved to be one of the most effective methods for low-power circuit design. Although sub-threshold circuits can obtain extremely large energy savings, their performance penalty is huge. In this paper, we propose a new adiabatic logic named as CAL-CPL (Clocked Adiabatic Logic with Complementary Pass-transistor Logic) circuit. The CAL-CPL circuit is similar to CAL (Clocked Adiabatic Logic) expect for its logic evaluation tree that is constructed by using CPL module to replace the NMOS logic tree of CAL. The characteristic of the CAL-CPL circuits is analyzed in term of energy dissipations. Then the energy dissipation and performance of the CAL-CPL circuits are investigated by lowing supply voltage from nominal voltage to near-threshold voltage. In the near-threshold region, the CAL-CPL circuits obtain considerable energy savings with a little performance penalty. A 4-2 compressor and 8421 BCD up-counter based on CAL-CPL circuits are realized and simulated using HSPICE at a 45 nm CMOS process with the NCSU PTM model. Simulation results show that the average power consumption of the near-threshold 4-2 compressor and 8421 BCD up-counter are reduced about 24% and 32% compared with the super-threshold ones for clock rates ranging from 50 MHz to 400 MHz, respectively. Therefore, the near-threshold computing of CAL-CPL circuits is an attractive approach especially suiting for mid performance low-power applications.