A Low-Power Multiplier Using Adiabatic CPL Circuits

Abstract

This paper investigates low-power characteristics of complementary pass-transistor logic (CPL) circuits using four-phase power-clocks. On this basis, adiabatic CPL circuits are introduced, which use bootstrapped NMOS switches to eliminate non-adiabatic loss of output loads. A tree multiplier using 4-2 compressor based on adiabatic CPL circuits is described. The energy loss of the adiabatic CPL circuits is closed to CPAL (complementary pass-transistor adiabatic logic) circuits. Its energy dissipation is less dependency on power-clock frequency and insensitivity to output load capacitance. Compared with the conventional CMOS implementation, the 4-2 compressor using adiabatic CPL circuits attains energy savings of 68% to 82% for clock rates ranging from 25 to 150 MHz.