Abstract
This paper presents the power optimization of complementary pass-transistor adiabatic logic (CPAL) and the design of adiabatic sequential circuits. CPAL circuits have more efficient energy transfer and recovery, because non-adiabatic energy loss of output loads has been completely eliminated by using complementary pass-transistor logic for evaluation and transmission gates for energy-recovery. The minimization of energy consumption was investigated by choosing the optimal size of transistors. Adiabatic flip-flops (D, T and JK) are introduced. A practical sequential system designed with the proposed adiabatic flip-flops was demonstrated. With TSMC 0.25/spl mu/m CMOS process, HSPICE simulation results show that the adiabatic flip-flop based on CPAL is about 2 to 3 times more energy efficient than 2N-2N2P and 3 to 6 times less dissipative than the static CMOS.
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