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Abstract
The silicon pixel detector is the innermost component of the CMS tracking system, providing high precision space point measurements of charged particle trajectories. The current pixel detector is designed to operate at a maximum luminosity of 1×1034 cm−2 s−1. Before 2018 the instantaneous luminosity of the LHC is expected to reach 2×1034 cm−2 s−1, which will significantly increase the number of interactions per bunch crossing. The performance of the current pixel detector in such high occupancy environment will be degraded due to substantial data-loss and effects of radiation damage of sensors, built up over the operational period. In order to maintain or exceed its current performance, the CMS pixel detector will be replaced by a new lightweight system with additional detection layers, better acceptance and improved readout electronics. The upgraded pixel detector will provide improved track and vertex reconstruction, standalone tracking capabilities, as well as identification of particles with longer lifetimes, which will be crucial elements of many physics analyses.
Highlights
In order to maintain or exceed its current performance, the CMS pixel detector will be replaced by a new lightweight system with additional detection layers, better acceptance and improved readout electronics
The services and the mechanical support structure of the current pixel detector introduce a non-negligible amount of material in the tracking volume, reducing the track reconstruction efficiency and degrading the impact parameter resolution
A high density interconnect (HDI) is glued on top of the sensor with wire-bond pads to connect to the cooresponding pads on the readout chip (ROC)
Summary
The current detector was designed to operate at a peak instantaneous luminosity of 1×1034cm−2s−1 and has performed very well during the first run of the LHC (2010-2012). Depending on the bunch spacing, the number of overlapping interactions per bunch crossing (referred to as pileup) will increase to 50 (25 ns bunch crossing time) or 100 (50 ns bunch crossing time) This leads to an increase in the track density and hit rates, with hit rates of up to 600 MHz cm−2 in the worst case in the innermost barrel layer. Under such conditions, the inefficiency in the readout chip would increase dramatically, from its current value of up to 4% to up to 16%, or even 50%, for bunch crossing intervals of 25 and 50 ns, respectively. The Phase-1 upgrade to the pixel detector is planned to accommodate these running conditions [3]
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