MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit

Abstract

This paper presents a low-power optimization technique (LPOT) for a 1V pipelined RISC microprocessor circuit via multi-threshold CMOS (MTCMOS) techniques. Using the MTCMOS LPOT, a 32-bit pipelined RISC microprocessor test circuit having 144,000 transistors with 3 stages per instruction has been optimized in terms of power consumption using standard threshold-SVT and high threshold-HVT logic cells. According to SPICE simulation results, during the 4-instruction GCD operation, the off-peak power consumption of this pipelined RISC CPU test circuit with the MTCMOS LPOT, designed using a 90nm CMOS technology, operating at 1V, has been reduced by 20% at the clock cycle of 1.35ns, as compared to the one using the conventional SVT one. The substantial saving on off-peak power consumption for the pipelined RISC CPU circuits via the MTCMOS LPOT could benefit for portable IT applications, where leakage power consumption is the key to battery life.