MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits

Abstract

This paper presents a low-power design technique (LPDT) for a low-voltage pipelined microprocessor circuit via multi-threshold CMOS (MTCMOS) techniques. Using the MTCMOS LPDT, a pipelined MIPS microprocessor circuit having 220,000 transistors with 5 stages per instruction has been optimized in terms of power consumption using standard threshold-SVT and high threshold-HVT logic cells. According to SPICE simulation results, during the 4-instruction compare operation, this pipelined CPU with the MTCMOS LPDT optimization, designed using a 90nm CMOS technology, operating at 1V and at a 1.3-ns clock period, has been reduced by 40.1% on the leakage power, 17.8% on the average total power and 13.3% on the peak power, as compared to the one using the conventional SVT one. The substantial saving in leakage power consumption for the pipelined CPU with the MTCMOS LPDT optimization could benefit for hand-held IT applications, where leakage power consumption is the key to battery life.