Abstract
In this paper, we report monolithic integration of two single-grain silicon layers for static random access memory (SRAM) and image sensor applications. A 12 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\times$</tex></formula> 28 silicon lateral photodiode array with a 25- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> pixel size prepared on top of a three-transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.
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