Modified 16 bit Carry Select and Carry Bypass Adder Architectures for High Speed Operations

Abstract

Adders are one of the most important block in an arithmetic logic unit. They are used everywhere from incrementing the value of program counter to high - end applications like digital signal processors. There are different adders with different propagation delay. Hence choosing an efficient adder is important for the optimum performance of a system. In this paper, different 16 bit adders which exist are compared in terms of their delay. Mathematical modelling of delay of logic gates have been done using logical effort in 180nm. This delay is then used to obtain the delay of different adders while simulating in ModelSim. Functional verification of adders have also been done using ModelSim. The path delay for each adder have also been found out using Xilinx ISE. In the light of this analysis, new carry bypass adder and carry select adder have been proposed to achieve less propagation delay. The proposed carry select adder and carry bypass adder shows a 45.42%, 16.5% decrease in combinational path delay and 20.4%, 29.5% decrease in logical effort delay respectively.