High-Speed 16-bit Carry Bypass Adder Design

Abstract

Adders are one of the most significant blocks in a logical arithmetic unit. These are employed in a wide range of applications, from incrementing the value of a program variable to high-speed applications such as video-encoding, digital-signal. There are various adders with varying propagation delays. As a result, selecting an efficient adder is critical for system performance. This research compares the latency of several 16 bit adders that are available. The delay of logic gates in 180nm technology has been quantitatively modelled utilizing logical effort. The delay is then utilized to calculate the delay of various adders in Virtuoso Cadence while simulating. Virtuoso Cadence was used to perform functional verification on adders. Each adder's route delay has also been determined. Based on this research, a new carry bypass adder has been developed to reduce propagation delay. The suggested carry bypass adder reduces combinational path latency by 7.2 percent and logical effort delay by 29.5 percent, respectively. Keywords: Algorithms for 16-bit adders, logical effort, propagation delay, carry skip adder