Modelling and testing for stuck faults in asymptotically zero power split-level charge recovery logic circuits

Abstract

A new transistor model is presented, which employs the LogicTransistor Function (LTF) to examine the behaviour of split-level Charge Recovery Logic (CRL) circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behaviour of the circuit can be identified from the fault-free LTF by using a systematic procedure. The model assumes; the logic values 0, 1, I and M, where I and M imply an intermediate logical value and a memory element respectively. Both classical stuck-at faults and non-classical transistor stuck faults are analyzed in the model. An algorithm based on a modified version of the Boolean difference technique is applied to obtain test vectors. Primitive D-cubes of the fault are extracted for a specific subcircuit. To generate tests for single or multiple faults, a variant of the D-algorithm may be used.