Modeling Feedback Bridging Faults with Non-Zero Resistance

Abstract

We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Moreover, the resistance intervals in which a particular behavior is observed are not necessarily contiguous. We demonstrate non-trivial behavior for situations in which a detection seems impossible, namely disabled loops going through a gate with controlling values on its side inputs. We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. For sequential circuits, we describe additional difficulties caused by the need to account for implications on bridge behavior, which have originated in the previous time frames. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.