Impact of Resistive Open and Bridge Defects on the SET Robustness of Standard CMOS Combinational Logic

Abstract

The robustness of standard CMOS combinational logic gates to Single Event Transients (SETs), in the presence of resistive open and resistive bridge defects, was investigated. Analysis was performed with SPICE simulations, using the resistors for modeling the open and bridge defects, and a standard double-exponential current source for modeling the SET effects. Two simple circuits based on NAND gate, designed in IHP's 130 nm bulk CMOS process, were employed for this study. It was demonstrated that, for certain input logic levels, the intra- and inter-gate resistive open and bridge defects may lead to significant decrease of the gate's critical charge, and thus to the increase of its soft error rate (SER) by more than one order of magnitude. Also, it was shown that the SET pulse width may significantly increase due to the resistive defects. Simulation results have confirmed that the resistive open defects have a stronger impact on the SET robustness of standard logic gates than the resistive bridge defects.