Modeling feedback bridging faults with non-zero resistance

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We study the behavior of feedback bridging faults with nonzero bridge resistance. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Even loops going through a gate with controlling values on its side inputs (which we call disabled loops) expose non-trivial behavior We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depend on the bridge resistance, making such a fault very hard to resolve. We conclude that the complexity of resistive feedback bridging fault simulation, accurate enough to resolve such situations, will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.