Modeling and simulation of Cu TSV electroplating for wafer-level MEMS vacuum packaging

Abstract

3D integration and packaging with through silicon via (TSV) is a promising method to overcome the limitation of integration scale in Micro-Electro-Mechanical Systems (MEMS) packaging. It is helpful to realize high density and reliability micro-devices. The technology of fabricating copper (Cu) TSVs by electroplating is applied to provide signal connection in vertical direction. However, the fabrication of defect-free and economical TSV is our destination. In this paper, the Cu deposition mechanism was analyzed and the process was expressed by a series of electrochemical equations. Finite element models (FEM) were built to simulate the double-sides Cu electroplating processes in wafer-level TSVs. Part of the 370μm thick and 100mm diameter double-sides polished silicon wafer model was built in the simulation. Simulation results show that defect-free Cu TSVs were achieved using optimized double-sided electroplating methods. Additives added in electrolyte affected the Cu deposition velocity and direction to a certain extent. Comparing to other common electroplating methods, double-sided electroplating was economy. Finally, Cu TSVs were successfully fabricated and applied to the vacuum packaging of MEMS.