Simulation and fabrication of two Cu TSV electroplating methods for wafer-level 3D integrated circuits packaging

Abstract

Three-dimensional (3-D) integration and packaging with through silicon via (TSV) is an emerging trend for overcoming the limitation of integration scale in Micro-electro-mechanical systems (MEMS) packaging. It is helpful for the realization of high density and reliability of micro-devices and sensors. The technology of fabricating copper (Cu) TSVs by electroplating is applied to provide communication links in vertical direction. The fabrication of defect-free and time-saving TSV is our destination. In this paper, the Cu deposition mechanism was analyzed and the process was expressed by a series of electrochemical equations. Finite element models were built to simulate two different kinds of Cu electroplating processes in through-hole via. 100mm diameter and 370μm thick polished silicon wafers were chosen in experiments. Under the guidance of the simulation results, defect-free Cu TSVs were obtained by using double-sided and bottom-up electroplating methods respectively. Electrolyte additives affected the Cu deposition velocity and direction to a certain extent. Comparing the two electroplating methods, we found that double-sided electroplating is economical and time-saving. While, bottom-up electroplating has the capability in filling the through-holes whose aspect ratio are greater than 10:1. It only took about 2.5h and 3.5h to obtain the intact Cu TSVs by using double-sided and bottom-up electroplating methods respectively. Finally, Cu TSVs were successfully applied to the Wafer Level Packaging (WLP) Pirani vacuum gauges for the vacuum packaging of MEMS. The vertical leakage rate of bonding samples ranged from 1.0E-9Pam3/s to 4.5E-8Pam3/s, which were measured by helium leak detector.