Methodology to Quantify Impact of Package Delamination on Performance of High-Side Smart Power Switch Design

Abstract

Abstract Generally, IC packages with exposed pads have excellent thermal and electrical performance – assuming high fidelity and integrity of die attach material. However, reliability challenges associated with die attach impacts electrical performance of vertical power FETs for high-side power switches. As such, it is critical to quantify the impact of these challenges on high-side power switches operation, so that their protection and diagnostic feature circuitries can be properly designed for mission critical applications. In this paper we present on a package and PCB co-modeling methodology that was developed to assess impact of die attach integrity on performance of high-side power switch designs. We explain how electrical co-optimization of the system (viz. FET-Package-PCB) interactions, was achieved through a coupled circuit-to-electromagnetic modeling, simulation, and analysis methodology. Silicon laboratory measurements data that validate the modeling methodology will be presented.