A High-reliability Half-Bridge GaN FET Gate Driver with Advanced Floating Bias Control Techniques

Abstract

The advanced floating bias control techniques (FBCT) for GaN devices are proposed in this paper, which aims at solving negative voltage transient issues present at switching node of power stage during dead time. It adopts maximum power-supply tracking to reduce time delay of level shifter and active clamping for bootstrap voltage to avoid overvoltage conditions. This high-reliability half-bridge GaN gate driver has been fabricated in a 0.5μ m 80V HV CMOS process and occupies a chip area of 1699×1522μ m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> where the active area of FBCT with internal bootstrap diode is 1350×620μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The response time of level shifter is only 1.97ns in the process of turning on high-side power switch. Transmission delay is small and there are no logic errors or latch-up issues in the gate driver due to the negative voltage transient. Bootstrap voltage ripple based on active clamping technique is well controlled over a wide frequency range (166mV@500kHz~ 797mV@5MHz at Cboot=0.1μF). The total quiescent current consumed by FBCT is only 90μ A.