MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic

Akhilesh Jaiswal,Kaushik Roy

doi:10.1038/srep39793

Abstract

In the quest for novel, scalable and energy-efficient computing technologies, many non-charge based logic devices are being explored. Recent advances in multi-ferroic materials have paved the way for electric field induced low energy and fast switching of nano-magnets using the magneto-electric (ME) effect. In this paper, we propose a voltage driven logic-device based on the ME induced switching of nano-magnets. We further demonstrate that the proposed logic-device, which exhibits decoupled read and write paths, can be used to construct a complete logic family including XNOR, NAND and NOR gates. The proposed logic family shows good scalability with a quadratic dependence of switching energy with respect to the switching voltage. Further, the proposed logic-device has better robustness against the effect of thermal noise as compared to the conventional current driven switching of nano-magnets. A device-to-circuit level coupled simulation framework, including magnetization dynamics and electron transport model, has been developed for analyzing the present proposal. Using our simulation framework, we present energy and delay results for the proposed Magneto-Electric Spin Logic (MESL) gates.

Highlights

Spin based logic devices are a promising candidate for beyond-CMOS technologies due to 1) non-volatility and low leakage power consumption and 2) area-efficiency
We demonstrate that our proposed logic-device can function as XNOR, NAND and NOR gate based on the configuration and show that easy cascadability can be achieved by using minimal number of CMOS devices
We demonstrate that the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, USA

Summary

ME Logic Family and Cascadability

A positive voltage represents a digital ‘1’ and a negative voltage represents a digital ‘0’ If, both the inputs are the same, the two nano-magnets will either point in +x direction or in −x direction and the MTJ stack would be in the low resistance (parallel) state. We do a reset operation by application of a negative voltage pulse so that all the magnets point in the −x direction This can be achieved by applying a negative voltage on input terminals ‘A’, ‘B’ and ‘C’, as shown in the timing diagram of Fig. 3. A reset operation is carried out by applying negative voltage pulses on terminals ‘A’, ‘B’, ‘C’, ‘G1’ and ‘G2’. Though, clocking is necessary for functioning of the proposed gates, it has been used in almost all non-volatile spin logic to reduce leakage power consumption[6,11]

Modeling and Simulation

FL mz z

Device Characteristics

Results and Discussions

Conclusions

Additional Information