Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design

Abstract

The development of the nanotechnology leads to the shrinking of the size of the transistors to nanometer region. However, there are a lot of challenges due to size scaling of the transistors such as short channel effects (SCEs) and threshold voltage roll-off issues. Fin-Type Field Effect Transistor (FinFET) is another alternative technology to solve the issues of the conventional MOSFET and increase the performance of the Static Random Access Memory (SRAM) circuit design. FinFET based SRAMs are faster and more reliable which are often used as memory cache for high speed operation. However, 6T SRAM cell suffers from access transistor sizing conflict resulting in a trade-off between read and write stability. This paper presents an investigation of the stability performance in retention, read and write mode of 22nm FinFET based 8T SRAM cell. The performance comparison of 22nm FinFET based 6T and 8 $T$ SRAMs were made. The simulation of the SRAM model are carried out in GTS Framework TCAD tool based on 22nm technology. In 8 $T$ SRAM cell, two n-FinFETs are added to the conventional 6 $T$ SRAM cell which will be controlled by the Read Word Line (RWL) to isolate the read and write operation path for better read stability. FinFET based 8T SRAM cell gives better performance in Static Noise Margin (SNM) and power consumption than 6T SRAM cells. The simulation results affirms the proposed FinFET based 8T SRAM improved read static noise margin by 166.67% and power consumption by 76.13% as compared to the FinFET based 6T SRAM.