Low-power fast-update pipelined phase accumulator for CML-based high-speed CMOS DDFSs

Abstract

Presented is a phase accumulator (PACC) for current-mode logic (CML)-based high-speed CMOS direct digital frequency synthesisers (DDFSs). The proposed PACC not only consumes low power by using an adaptive power reduction technique, but also updates frequency information within one clock period by using dual function logic gates and the charge sharing scheme that accelerates current recovery time. This work reduces power consumption by 33% compared to the conventional PACC with a pipeline depth of 8 and 32-bit FCW.