Area and Power Efficient Architecture for Direct Digital Frequency Synthesizer

Abstract

Direct Digital Frequency Synthesis (DDFS) is a technique of creating analogue waveform by digitally modifying a fixed system clock and then processing the output through a DAC (Digital-to-Analog Converter). This enables for fine frequency resolution throughout a wide range of frequencies, as well as rapid switching between them. Rapid frequency switching, big bandwidth, fine frequency resolution and superb spectral purity are only a few of the benefits. Also, as a critical component for next-generation radar and communication systems, high frequency resolution, high speed and a fast frequency channel have formed as requirements for designing a new DDFS system. A Phase Accumulator (PA), a ROM/look-up table, a DAC, and certain reconstruction filters make up a conventional DDFS archi-tecture. For improving the spectral purity of output sine wave, a large ROM and high-resolution DAC are usually necessary. Large ROM look-up tables, on the other hand, result in increased power consumption, slower access times, reduced reliability and a bigger die size. DDFS products are quickly replacing traditional frequency agile analogue synthesizer solutions due to their low cost, excellent performance, functional integration, and small package footprint. Because of the enormous demand for such systems, integrating a high-speed, high-performance DAC and DDFS architecture onto minimum hardware becomes critical. This proposed work aims to design and implement the DDFS with improvised performance in terms of power consumption and area by applying techniques such as quarter wave symmetry, memory-less ROM and pipelined phase accumulator with Kogge-Stone adder. Quarter wave symmetry reduces the bit size requirement of ROM by 75% as it uses only quarter of the wave to reconstruct the full sine wave. ROM architecture applied in this work consists of simple logic gates only, which reduces the ROM size significantly also reducing the power dissipation. Pipelined architecture of the PA improves the performance the DDFS because of its parallel operation.